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ISL1220
I2C(R) Real Time Clock/Calendar with Frequency Output
Data Sheet June 22, 2006 FN6315.0
Low Power RTC with 8 Bytes of Battery Backed SRAM and Separate FOUT
The ISL1220 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, battery-backed user SRAM and separate FOUT and IRQ outputs. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.
Features
* Real Time Clock/Calendar - Tracks Time in Hours, Minutes, and Seconds - Day of the Week, Day, Month, and Year * Frequency Output pin - 15 Selectable Output Frequencies * Single Alarm with Separate Interrupt pin - Settable to the Second, Minute, Hour, Day of the Week, Day, or Month - Single Event or Pulse Interrupt Mode * Automatic Backup to Battery or Super Cap * Power Failure Detection
Ordering Information
PART NUMBER (Note) ISL1220IUZ PART MARKING 1220Z VDD RANGE TEMP. RANGE (C) PACKAGE (Pb-Free)
* On-Chip Oscillator Compensation * 8 Bytes Battery-Backed User SRAM * I2C Interface - 400kHz Data Transfer Rate * 400nA Battery Supply Current * Small Package Option - 10 Ld MSOP Package * Pb-Free Plus Anneal Available (RoHS Compliant)
2.7V to 5.5V -40 to +85 10 Ld MSOP 2.7V to 5.5V -40 to +85 10 Ld MSOP Tape and Reel
ISL1220IUZ-T 1220Z
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Applications
* Utility Meters * HVAC Equipment
Pinout
ISL1220 (10 LD MSOP) TOP VIEW
X1 X2 VBAT GND NC 1 2 3 4 5 10 VDD 9 8 7 6 IRQ SCL SDA FOUT
* Audio/Video Components * Set Top Box/Television * Modems * Network Routers, Hubs, Switches, Bridges * Cellular Infrastructure Equipment * Fixed Broadband Wireless Equipment * Pagers/PDA * POS Equipment * Test Meters/Fixtures * Office Automation (Copiers, Fax) * Home Appliances * Computer Products * Other Industrial/Medical/Automotive
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL1220 Block Diagram
SDA SCL SDA BUFFER SCL BUFFER I2C INTERFACE SECONDS CONTROL LOGIC MINUTES HOURS DAY OF WEEK X1 X2 VDD CRYSTAL OSCILLATOR RTC DIVIDER DATE MONTH POR VTRIP SWITCH VBAT INTERNAL SUPPLY FREQUENCY OUT YEAR ALARM CONTROL REGISTERS USER SRAM
IRQ
GND FOUT
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 SYMBOL X1 X2 VBAT GND NC FOUT SDA SCL IRQ VDD DESCRIPTION The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Ground. No Connection Frequency Output (FOUT). Open drain output, Programmable to be active/disabled in battery back up mode. Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR'ed with other open drain or open collector outputs. The Serial Clock (SCL) input is used to clock all serial data into and out of the device. Interrupt Output. Open drain output, active low. Power supply.
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Absolute Maximum Ratings
Voltage on VDD, VBAT, SCL, SDA, and IRQ, FOUT Pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Voltage on X1 and X2 Pins (respect to ground) . . . . . . . . . . . .-0.5V to VDD + 0.5 (VDD Mode) -0.5V to VBAT + 0.5 (VBAT Mode) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . .>2kV ESD Rating (Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . .>175V Output Current Sink (FOUT, IRQ . . . . . . . . . . . . . . . . . . . . . . . . 3mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 120 Moisture Sensitivity (see Technical Brief TB363). . . . . . . . . . Level 2 Maximum Junction Temperature (Plastic Package). . . . . . . . . 150C
Recommended Operating Conditions
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C VDD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V VBAT Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Characteristics - RTC Temperature = -40C to +85C, unless otherwise stated.
SYMBOL VDD VBAT IDD1 PARAMETER Main Power Supply Battery Supply Voltage Supply Current VDD = 5V VDD = 3V IDD2 IDD3 IBAT IBATLKG ILI ILO VTRIP VTRIPHYS VBATHYS IRQ, FOUT VOL Output Low Voltage VDD = 5V, IOL = 3mA VDD = 2.7V, IOL = 1mA ILO Output Leakage Current VDD = 5.5V VOUT = 5.5V 100 0.4 0.4 400 V V nA Supply Current with I2C Active Supply Current (Low Power Mode) Battery Supply Current Battery Input Leakage Input Leakage Current on SCL I/O Leakage Current on SDA VBAT Mode Threshold VTRIP Hysteresis VBAT Hysteresis 1.6 10 10 VDD = 5V VDD = 5V, LPMODE = 1 VBAT = 3V VDD = 5.5V, VBAT = 1.8V 100 100 2.2 35 50 2.64 60 100 CONDITIONS MIN 2.7 1.8 2 1.2 40 1.4 400 TYP (Note 5) MAX 5.5 5.5 6 4 120 5 950 100 UNITS V V A A A A nA nA nA nA V mV mV 2, 3 2, 7 2 2, 3 NOTES
Power-Down Timing Temperature = -40C to +85C, unless otherwise stated.
SYMBOL VDD SRPARAMETER VDD Negative Slewrate Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS MIN TYP (Note 5) MAX UNITS NOTES CONDITIONS MIN TYP (Note 5) MAX 10 UNITS V/ms NOTES 4
Serial Interface Specifications
SYMBOL PARAMETER
SERIAL INTERFACE SPECS VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V
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Serial Interface Specifications
SYMBOL VIH PARAMETER SDA and SCL Input Buffer HIGH Voltage Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS MIN 0.7 x VDD 0.05 x VDD 0 TA = 25C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. Measured at the 30% of VDD crossing. Measured at the 70% of VDD crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. From 30% to 70% of VDD From 70% to 30% of VDD Total on-chip and off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k. For Cb = 40pF, max is about 15~20k 1300 0.4 10 400 50 900 TYP (Note 5) MAX VDD + 0.3 UNITS V V V pF kHz ns ns ns NOTES
Hysteresis SDA and SCL Input Buffer Hysteresis VOL Cpin fSCL tIN tAA tBUF SDA Output Buffer LOW Voltage, Sinking 3mA SDA and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Time the Bus Must be Free before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT
Input Data Hold Time
0
900
ns
tSU:STO tHD:STO tDH
STOP Condition Setup Time STOP condItion Hold Time Output Data Hold Time
600 600 0
ns ns ns
tR tF Cb Rpu
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip
20 + 0.1 x Cb 20 + 0.1 x Cb 10 1
300 300 400
ns ns pF k
6 6 6 6
NOTES: 2. IRQ and FOUT Inactive. 3. LPMODE = 0 (default). 4. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 5. Typical values are for T = 25C and 3.3V supply voltage. 6. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification. 7. A write to register 08h should only be done if VDD > VBAT, otherwise the device will be unable to communicate using I2C.
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ISL1220 SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
Symbol Table
WAVEFORM INPUTS Must be steady OUTPUTS Will be steady
May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A
Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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ISL1220 Typical Performance Curves Temperature is +25C unless otherwise specified
1E-6 900E-9 800E-9 700E-9 IBAT (A) IBAT (A) 1.5 2.0 2.5 3.0 3.5 4.0 VBAT (V) 4.5 5.0 5.5 600E-9 500E-9 400E-9 300E-9 200E-9 100E-9 000E+0 000E+0 -40 -20 0 20 40 TEMPERATURE (C) 60 80 200E-9 600E-9 800E-9 1E-6
400E-9
FIGURE 1. IBAT vs VBAT
FIGURE 2. IBAT vs TEMPERATURE AT VBAT = 3V
2.4E-06 2.2E-06 VCC = 5V 2.0E-06 IDD1 (A) 1.8E-06 1.6E-06 VCC = 3.3V 1.4E-06 1.2E-06 1.0E-06 -40 -20 0 20 40 60 80 IDD1 (A)
2.4E-6 2.2E-6 2.0E-6 1.8E-6 1.6E-6 1.4E-6 1.2E-6 1.0E-6 800.0E-9 600.0E-9 400.0E-9 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 LPMODE = 1 LPMODE = 0
TEMPERATURE (C)
FIGURE 3. IDD1 vs TEMPERATURE
FIGURE 4. IDD1 vs VCC WITH LPMODE ON AND OFF
2.1E-6 2.0E-6 1.9E-6 IDD1 (A) 1.8E-6 1.7E-6 1.6E-6 1.5E-6 1.4E-6 1.3E-6 1/4 1/2 1 1/32 1/16 1/8 2 4 8 16 32 64 1024 4096 32768 1.2E-6 IDD1 (A)
1/32
1/16
1/4
1/2
1
1/8
2
4
8
16
32
64
1024
4096
FOUT (Hz)
FOUT (Hz)
FIGURE 5. IDD1 vs FOUT AT VDD = 3.3V
FIGURE 6. IDD1 vs FOUT AT VDD = 5V
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32768
3.0E-6 2.9E-6 2.8E-6 2.7E-6 2.6E-6 2.5E-6 2.4E-6 2.3E-6 2.2E-6 2.1E-6 2.0E-6 1.9E-6 1.8E-6
ISL1220
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533 SDA AND IRQ, FOUT FOR VOL= 0.4V AND IOL = 3mA X1 X2
100pF
FIGURE 8. RECOMMENDED CRYSTAL CONNECTION
VBAT
FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V
General Description
The ISL1220 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, battery-backed user SRAM and separate FOUT and IRQ outputs. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. The ISL1220's powerful alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or Super Cap with automatic switchover from VDD to VBAT. The entire ISL1220 device is fully operational from 2.0V to 5.5V and the clock/calendar portion of the device remains fully operational down to 1.8V (Standby Mode).
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used.
IRQ (Interrupt Output)
The IRQ output is an open drain active low configuration. * Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated.
FOUT (Frequency Output)
* Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain active low output.
Pin Description
X1, X2
The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1220 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40C to +85C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. The device can also be driven directly from a 32.768kHz source at pin X1.
VDD, GND
Chip power supply and ground pins. The device will operate with a power supply from 2.0V to 5.5VDC. A 0.1F capacitor is recommended on the VDD pin to ground.
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL1220 for up to 10 years. Another option is to use a
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Super Cap for applications where VDD is interrupted for up to a month. See the Applications Section for more information. The I2C bus is deactivated in battery backup mode to provide lower power. Aside from this, all RTC functions are operational during battery backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL1220 are active during battery backup mode unless disabled via the control register. The User SRAM is operational in battery backup mode down to 2V.
Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS 50mV Condition 2: VDD < VTRIP where VTRIP 2.2V
Power Failure Detection
The ISL1220 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT).
Low Power Mode
The normal power switching of the ISL1220 is designed to switch into battery backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Another mode, called Low Power Mode, is available to allow direct switching from VDD to VBAT without requiring VDD to drop below VTRIP. Since the additional monitoring of VDD vs VTRIP is no longer needed, that circuitry is shut down and less power is used while operating from VDD. Power savings are typically 600nA at VDD = 5V. Low Power Mode is activated via the LPMODE bit in the control and status registers. Low Power Mode is useful in systems where VDD is normally higher than VBAT at all times. The device will switch from VDD to VBAT when VDD drops below VBAT, with about 50mV of hysteresis to prevent any switchback of VDD after switchover. In a system with a VDD = 5V and backup lithium battery of VBAT = 3V, Low Power Mode can be used. However, it is not recommended to use Low Power Mode in a system with VDD = 3.3V 10%, VBAT 3.0V, and when there is a finite I-R voltage drop in the VDD line.
Battery Backup Mode (VBAT) to Normal Mode (VDD)
The ISL1220 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS 50mV Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS 30mV These power control situations are illustrated in Figures 9 and 10.
VDD VTRIP VBAT VBAT - VBATHYS
BATTERY BACKUP MODE
2.2V 1.8V VBAT + VBATHYS
InterSealTM Battery Saver
The ISL1220 has the InterSealTM Battery Saver which prevents initial battery current drain before it is first used. For example, battery-backed RTCs are commonly packaged on a board with a battery connected. In order to preserve battery life, the ISL1220 will not draw any power from the battery source until after the device is first powered up from the VDD source. Thereafter, the device will switchover to battery backup mode whenever VDD power is lost.
FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP
VDD VBAT VTRIP VTRIP
BATTERY BACKUP MODE
Real Time Clock Operation
3.0V 2.2V
VTRIP + VTRIPHYS
FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP
The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL1220 powers up after the loss of both VDD and VBAT, the clock will
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ISL1220
not begin incrementing until at least one byte is written to the clock register.
I2C Serial Interface
The ISL1220 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bidirectional data signal (SDA) and a clock signal (SCL).
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal's nominal frequency. For example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. These parameters are available from the crystal manufacturer. The ISL1220 provides on-chip crystal compensation networks to adjust load capacitance to tune oscillator frequency from -94ppm to +140ppm. For more detailed information see the Application Section.
Oscillator Compensation
The ISL1220 provides the option of timing correction due to temperature variation of the crystal oscillator for either manufacturing calibration or active calibration. The total possible compensation is typically -94ppm to +140ppm. Two compensation mechanisms that are available are as follows: 1. An analog trimming (ATR) register that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. The individual digital capacitor is selectable from a range of 9pF to 40.5pF (based upon 32.758kHz). This translates to a calculated compensation of approximately -34ppm to +80ppm. (See ATR description.) 2. A digital trimming register (DTR) that can be used to adjust the timing counter by 60ppm. (See DTR description.) Also provided is the ability to adjust the crystal capacitance when the ISL1220 switches from VDD to battery backup mode. (See Battery Mode ATR Selection for more details.)
Single Event and Interrupt
The alarm mode is enabled via the ALME bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, an IRQ pin will be pulled low and the alarm status bit (ALM) will be set to "1". The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ pin will be pulled low for 250ms and the alarm status bit (ALM) will be set to "1". The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). The alarm function can be enabled/disabled during battery backup mode using the FOBATB bit. For more information on the alarm, please see the Alarm Registers Description.
Register Descriptions
The battery-backed registers are accessible following a slave byte of "1101111x" and reads or writes to addresses [00h:19h]. The defined addresses and default values are described in the Table 1. Address 09h is not used. Reads or writes to 09h will not affect operation of the device but should be avoided. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 4 sections. These are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Control and Status (5 bytes): Address 07h to 0Bh. 3. Alarm (6 bytes): Address 0Ch to 11h. 4. User SRAM (8 bytes): Address 12h to 19h. There are no addresses above 19h.
Frequency Output Mode
The ISL1220 has the option to provide a frequency output signal using the FOUT pin. The frequency output mode is set by using the FO bits to select 15 possible output frequency values from 0 to 32kHz. The frequency output can be enabled/disabled during battery backup mode using the FOBATB bit.
General Purpose User SRAM
The ISL1220 provides 8 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However, it should be noted that the I2C bus is disabled in battery backup mode.
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Write capability is allowable into the RTC registers (00h to 06h) only when the WRTC bit (bit 4 of address 07h) is set to "1". A multi-byte read or write operation is limited to one section per operation. Access to another section requires a new operation. A read or write can begin at any address within the section. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. It is not necessary to set the WRTC bit prior to writing into the control and status, alarm, and user SRAM registers.
TABLE 1. REGISTER MEMORY MAP REG ADDR. SECTION NAME 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh Alarm 0Fh 10h 11h 12h 13h 14h 15h User 16h 17h 18h 19h USR5 USR6 USR7 USR8 USR57 USR67 USR77 USR87 USR56 USR66 USR76 USR86 USR55 USR65 USR75 USR85 USR54 USR64 USR74 USR84 USR53 USR63 USR73 USR83 USR52 USR62 USR72 USR82 USR51 USR61 USR71 USR81 USR50 USR60 USR70 USR80 N/A N/A N/A N/A 00h 00h 00h 00h DTA MOA DWA USR1 USR2 USR3 USR4 EDTA EMOA EDWA USR17 USR27 USR37 USR47 0 0 0 USR16 USR26 USR36 USR46 ADT21 0 0 USR15 USR25 USR35 USR45 ADT20 AMO20 0 USR14 USR24 USR34 USR44 ADT13 AMO13 0 USR13 USR23 USR33 USR43 ADT12 AMO12 ADW12 USR12 USR22 USR32 USR42 ADT11 AMO11 ADW11 USR11 USR21 USR31 USR41 ADT10 AMO10 ADW10 USR10 USR20 USR30 USR40 1-31 1-12 0-6 N/A N/A N/A N/A 00h 00h 00h 00h 00h 00h 00h Control and Status RTC SC MN HR DT MO YR DW SR INT BIT 7 0 0 MIL 0 0 YR23 0 ARST IM 6 SC22 MN22 0 0 0 YR22 0 5 SC21 MN21 HR21 DT21 0 YR21 0 4 SC20 MN20 HR20 DT20 MO20 YR20 0 WRTC FOBATB Reserved ATR DTR SCA MNA HRA BMATR1 Reserved ESCA EMNA EHRA ASC22 AMN22 0 ASC21 AMN21 AHR21 ASC20 AMN20 AHR20 ASC13 AMN13 AHR13 BMATR0 ATR5 ATR4 ATR3 ATR2 DTR2 ASC12 AMN12 AHR12 ATR1 DTR1 ASC11 AMN11 AHR11 ATR0 DTR0 ASC10 AMN10 AHR10 3 SC13 MN13 HR13 DT13 MO13 YR13 0 Reserved FO3 2 SC12 MN12 HR12 DT12 MO12 YR12 DW2 ALM FO2 1 SC11 MN11 HR11 DT11 MO11 YR11 DW1 BAT FO1 0 SC10 MN10 HR10 DT10 MO10 YR10 DW0 RTCF FO0 RANGE 0-59 0-59 0-23 1-31 1-12 0-99 0-6 N/A N/A N/A N/A N/A 00-59 00-59 0-23 DEFAULT 00h 00h 00h 00h 00h 00h 00h 01h 00h 00h 00h 00h 00h 00h 00h
XTOSCB Reserved ALME LPMODE
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ISL1220 Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the Week) is 0 to 6. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-... The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as "0". 24 HOUR TIME If the MIL bit of the HR register is "1", the RTC uses a 24-hour format. If the MIL bit is "0", the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a "1" representing PM. The clock defaults to 12-hour format time with HR21 = "0". LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL1220 does not correct for the leap year in the year 2100. REAL TIME CLOCK FAIL BIT (RTCF) This bit is set to a "1" after a total power failure. This is a read only bit that is set by hardware (ISL1220 internally) when the device powers up after having lost all power to the device. The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to "1". The first valid write to the RTC section after a complete power failure resets the RTCF bit to "0" (writing one byte is sufficient). BATTERY BIT (BAT) This bit is set to a "1" when the device enters battery backup mode. This bit can be reset either manually by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to "0", not "1". ALARM BIT (ALM) These bits announce if the alarm matches the real time clock. If there is a match, the respective bit is set to "1". This bit can be manually reset to "0" by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to "0", not "1".
NOTE: An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete.
WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is "0". Upon initialization or power up, the WRTC must be set to "1" to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB) This bit enables/disables the internal crystal oscillator. When the XTOSCB is set to "1", the oscillator is disabled, and the X1 pin allows for an external 32kHz signal to drive the RTC. The XTOSCB bit is set to "0" on power-up. AUTO RESET ENABLE BIT (ARST) This bit enables/disables the automatic reset of the BAT and ALM status bits only. When ARST bit is set to "1", these status bits are reset to "0" after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to "0", the user must manually reset the BAT and ALM bits.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers.
Status Register (SR)
The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or status of RTC failure, battery mode, alarm trigger, write protection of clock counter, crystal oscillator enable and auto reset of status bits.
TABLE 2. STATUS REGISTER (SR) ADDR 07h Default 7 6 5 4 3 2 1 0
ARST XTOSCB reserved WRTC reserved ALM BAT RTCF 0 0 0 0 0 0 0 0
Interrupt Control Register (INT)
TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 08h Default 7 IM 0 6 5 4 3 2 1 0
ALME LPMODE FOBATB FO3 FO2 FO1 FO0 0 0 0 0 0 0 0
The interrupt control register contains Frequency Output, Alarm, and Battery switchover control bits.
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NOTE: Writing to register 08h has restrictions. If VBAT>VDD, then no byte writes to register 08h are allowed, only page writes beginning with register 07h. If VDD>VBAT, then a byte write to register 08h IS allowed, as well as page writes.
(See Typical Performance Curves: IDD vs VCC with LPMODE ON AND OFF.) ALARM ENABLE BIT (ALME) This bit enables/disables the alarm function. When the ALME bit is set to "1", the alarm function is enabled. When the ALME is cleared to "0", the alarm function is disabled. The alarm function can operate in either a single event alarm or a periodic interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function is disabled.
FREQUENCY OUT CONTROL BITS (FO <3:0>) These bits enable/disable the frequency output function and select the output frequency at the FOUT pin. See Table 4 for frequency selection. If all bits are set to Zero, the FOUT function is disabled.
TABLE 4. FREQUENCY SELECTION OF FOUT PIN FREQUENCY, FOUT UNITS 0 32768 4096 1024 64 32 16 8 4 2 1 1/2 1/4 1/8 1/16 1/32 Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz FO3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FO2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FO1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FO0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
INTERRUPT/ALARM MODE BIT (IM) This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to "1", the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ pin when the RTC is triggered by the alarm as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to "0", the alarm will operate in standard mode, where the IRQ pin will be tied low until the ALM status bit is cleared to "0".
IM BIT 0 1 INTERRUPT/ALARM FREQUENCY Single Time Event Set By Alarm Repetitive/Recurring Time Event Set By Alarm
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
X1
0 1
X2
CX1
CRYSTAL OSCILLATOR
FREQUENCY OUTPUT BIT (FOBATB) This bit enables/disables the FOUT pin during battery backup mode (i.e. VBAT power source active). When the FOBATB is set to "1" the FOUT pin is disabled during battery backup mode. This means the frequency output function is disabled. When the FOBATB is cleared to "0", the FOUT pin is enabled during battery backup mode. The FOUT pin is open drain output and requires a pull up resistor to VBAT for operation in battery backup mode LOW POWER MODE BIT (LPMODE) This bit enables/disables low power mode. With LPMODE = "0", the device will be in normal mode and the VBAT supply will be used when VDD < VBAT - VBATHYS and VDD < VTRIP. With LPMODE = "1", the device will be in low power mode and the VBAT supply will be used when VDD < VBAT - VBATHYS. There is a supply current saving of about 600nA when using LPMODE = "1" with VDD = 5V.
CX2
FIGURE 11. DIAGRAM OF ATR
Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34 to +80ppm to the nominal frequency compensation. The combination of analog and digital trimming can give up to -94 to +140ppm of total adjustment. The effective on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a mid-scale value of
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12.5pF (default). CLOAD is changed via two digitally controlled capacitors, CX1 and CX2, connected from the X1 and X2 pins to ground (see Figure 11). The value of CX1 and CX2 is given by the following formula:
C X = ( 16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 )pF
TABLE 6. DIGITAL TRIMMING REGISTERS DTR REGISTER DTR2 0 0 0 0 1 1 1 1 DTR1 0 0 1 1 0 0 1 1 DTR0 0 1 0 1 0 1 0 1 ESTIMATED FREQUENCY PPM 0 (default) +20 +40 +60 0 -20 -40 -60
The effective series load capacitance is the combination of CX1 and CX2:
C LOAD = ---------------------------------X1 X2
1 1 1 ---------- + ---------- C C
16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 = ---------------------------------------------------------------------------------------------------------------------------- pF C LOAD 2
For example, CLOAD(ATR = 00000) = 12.5pF, CLOAD(ATR=100000) = 4.5pF, and CLOAD(ATR=011111) = 20.25pF. The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. BATTERY MODE ATR SELECTION (BMATR <1:0>) Since the accuracy of the crystal oscillator is dependent on the VDD/VBAT operation, the ISL1220 provides the capability to adjust the capacitance between VDD and VBAT when the device switches between power sources.
TABLE 5. DELTA CAPACITANCE (CBAT TO CVDD) 0pF -0.5pF ( +2ppm) +0.5pF ( -2ppm) +1pF ( -4ppm)
Alarm Registers
Addresses [0Ch to 11h]
The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = "1"). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. There are two alarm operation modes: Single Event and periodic Interrupt Mode: * Single Event Mode is enabled by setting the ALME bit to "1", the IM bit to "0", and disabling the frequency output. This mode permits a one-time match between the alarm registers and the RTC registers. Once this match occurs, the ALM bit is set to "1" and the IRQ output will be pulled low and will remain low until the ALM bit is reset. This can be done manually or by using the auto-reset feature. * Interrupt Mode is enabled by setting the ALME bit to "1", the IM bit to "1", and disabling the frequency output. The IRQ output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. To clear an alarm, the ALM bit in the status register must be set to "0" with a write. Note that if the ARST bit is set to 1 (address 07h, bit 7), the ALM bit will automatically be cleared when the status register is read.
BMATR1 0 0 1 1
BMATR0 0 1 0 1
DIGITAL TRIMMING REGISTER (DTR <2:0>) The digital trimming bits DTR0, DTR1, and DTR2 adjust the average number of counts per second and average the ppm error to achieve better accuracy. * DTR2 is a sign bit. DTR2 = "0" means frequency compensation is >0. DTR2 = "1" means frequency compensation is <0. * DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm adjustment and DTR0 gives 20ppm adjustment. A range from -60ppm to +60ppm can be represented by using these three bits (see Table 6).
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Below are examples of both Single Event and periodic Interrupt Mode alarms. Example 1 - Alarm set with single interrupt (IM = "0") A single alarm will occur on January 1 at 11:30am. A. Set Alarm registers as follows:
ALARM REGISTER 7 SCA MNA HRA DTA MOA DWA 0 1 1 1 1 0 BIT 6 0 0 0 0 0 0 5 0 1 0 0 0 0 4 0 1 1 0 0 0 3 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 HEX DESCRIPTION
60 SEC
Once the registers are set, the following waveform will be seen at IRQ-:
RTC AND ALARM REGISTERS ARE BOTH "30" SEC
00h Seconds disabled B0h Minutes set to 30, enabled 91h Hours set to 11, enabled 81h Date set to 1, enabled 81h Month set to 1, enabled 00h Day of week disabled
Note that the status register ALM bit will be set each time the alarm is triggered, but does not need to be read or cleared.
User Registers
Addresses [12h to 19h]
These registers are 8 bytes of battery-backed user memory storage.
I2C Serial Interface
The ISL1220 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL1220 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
B. Also the ALME bit must be set as follows:
CONTROL REGISTER 7 INT 0 BIT 6 1 5 x 4 x 3 0 2 0 1 0 0 0 HEX x0h DESCRIPTION Enable Alarm
xx indicate other control bits After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the status register to "1" and also bringing the IRQ output low. Example 2 - Pulsed interrupt once per minute (IM = "1") Interrupts at one minute intervals when the seconds register is at 30 seconds. A. Set Alarm registers as follows:
BIT ALARM REGISTER 7 6 5 4 3 2 1 0 HEX SCA MNA HRA DTA MOA DWA
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 12). On power up of the ISL1220, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL1220 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 12). A START condition is ignored during the power-up sequence. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 12). A STOP condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the
DESCRIPTION
1 0 1 1 0 0 0 0 B0h Seconds set to 30, enabled 0 0 0 0 0 0 0 0 00h Minutes disabled 0 0 0 0 0 0 0 0 00h Hours disabled 0 0 0 0 0 0 0 0 00h Date disabled 0 0 0 0 0 0 0 0 00h Month disabled 0 0 0 0 0 0 0 0 00h Day of week disabled
B. Set the Interrupt register as follows:
BIT CONTROL REGISTER 7 6 5 4 3 2 1 0 HEX INT
DESCRIPTION
1 1 x x 0 0 0 0 x0h Enable Alarm and Int Mode
xx indicate other control bits 14
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receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 13). The ISL1220 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL1220 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation.
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 12. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL1220
11011110 A C K
0000 A C K A C K
FIGURE 14. BYTE WRITE SEQUENCE
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ISL1220 Device Addressing
Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifier. These bits are "1101111". Slave bits "1101" access the register. Slave bits "111" specify the device select bits. The last bit of the Slave Address Byte defines a read or write operation to be performed. When this R/W bit is a "1", then a read operation is selected. A "0" selects a write operation (Refer to Figure 15). After loading the entire Slave Address Byte from the SDA bus, the ISL1220 compares the device identifier and device select bits with "1101111". Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power up the internal address counter is set to address 0h, so a current address read of the CCR array starts at address 0h. When required, as part of a random read, the master must supply the 1 Word Address Bytes as shown in Figure 16. In a random read operation, the slave byte in the "dummy write" portion must match the slave byte in the "read" section. For a random read of the Clock/Control Registers, the slave byte must be "1101111x" in both places.
SLAVE ADDRESS BYTE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL1220 responds with an ACK. At this time, the I2C interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (See Figure 16). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL1220 responds with an ACK. Then the ISL1220 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 16). The Data Bytes are from the memory location indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 19h the pointer "rolls over" to 00h, and the device continues to output data for each ACK received.
1
1
0
1
1
1
1
R/W
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
S T IDENTIFICATION A BYTE WITH R R/W = 1 T
A C K
A C K
S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
11011110 A C K A C K
11011111 A C K
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 16. READ SEQUENCE
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ISL1220 Application Section
Oscillator Crystal Requirements
The ISL1220 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table 7 lists some recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be used with the ISL1220 if their specifications are very similar to the devices listed. The crystal should have a required parallel load capacitance of 12.5pF and an equivalent series resistance of less than 50k. The crystal's temperature range specification should match the application. Many crystals are rated for -10C to +60C (especially through hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required.
TABLE 7. SUGGESTED SURFACE MOUNT CRYSTALS MANUFACTURER Citizen Epson Raltron SaRonix Ecliptek ECS Fox PART NUMBER CM200S MC-405, MC-406 RSM-200S 32S12 ECPSM29T-32.768K ECX-306 FSM-327
In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the ISL1220. There are 3 bits known as the Digital Trimming Register (DTR). The range provided is 60ppm in increments of 20ppm. DTR operates by adding or skipping pulses in the clock counter. It is very useful for coarse adjustments of frequency drift over temperature or extending the adjustment range available with the ATR register. Initial accuracy is best adjusted by monitoring the frequency output at FOUT pin with a calibrated frequency counter. The frequency used is unimportant, although 1Hz is the easiest to monitor. The gating time should be set long enough to ensure accuracy to at least 1ppm. The ATR should be set to the center position, or 100000Bh, to begin with. Once the initial measurement is made, then the ATR register can be changed to adjust the frequency. Note that increasing the ATR register for increased capacitance will lower the frequency, and vice-versa. If the initial measurement shows the frequency is far off, it will be necessary to use the DTR register to do a coarse adjustment. Note that most all crystals will have tight enough initial accuracy at room temperature so that a small ATR register adjustment should be all that is needed.
Temperature Compensation
The ATR and DTR controls can be combined to provide crystal drift temperature compensation. The typical 32.768kHz crystal has a drift characteristic that is similar to that shown in Figure 17. There is a turnover temperature (T0) where the drift is very near zero. The shape is parabolic as it varies with the square of the difference between the actual temperature and the turnover temperature.
0.0
Crystal Oscillator Frequency Adjustment
The ISL1220 device contains circuitry for adjusting the frequency of the crystal oscillator. This circuitry can be used to trim oscillator initial accuracy as well as adjust the frequency to compensate for temperature changes. The Analog Trimming Register (ATR) is used to adjust the load capacitance seen by the crystal. There are six bits of ATR control, with linear capacitance increments available for adjustment. Since the ATR adjustment is essentially "pulling" the frequency of the oscillator, the resulting frequency changes will not be linear with incremental capacitance changes. The equations which govern pulling show that lower capacitor values of ATR adjustment will provide larger increments. Also, the higher values of ATR adjustment will produce smaller incremental frequency changes. These values typically vary from 6-10ppm/bit at the low end to <1ppm/bit at the highest capacitance settings. The range afforded by the ATR adjustment with a typical surface mount crystal is typically -34 to +80ppm around the ATR = 0 default setting because of this property. The user should note this when using the ATR for calibration. The temperature drift of the capacitance used in the ATR control is extremely low, so this feature can be used for temperature compensation with good accuracy.
-20.0 -40.0 -60.0 PPM -80.0 -100.0 -120.0 -140.0 -160.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (C)
FIGURE 17. RTC CRYSTAL TEMPERATURE DRIFT
If full industrial temperature compensation is desired in an ISL1220 circuit, then both the DTR and ATR registers will need to be utilized (total correction range = -94 to +140ppm). A system to implement temperature compensation would consist of the ISL1220, a temperature sensor, and a microcontroller. These devices may already be in the system
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so the function will just be a matter of implementing software and performing some calculations. Fairly accurate temperature compensation can be implemented just by using the crystal manufacturer's specifications for the turnover temperature T0 and the drift coefficient (). The formula for calculating the oscillator adjustment necessary is: Adjustment (ppm) = (T - T0)2 * Once the temperature curve for a crystal is established, then the designer should decide at what discrete temperatures the compensation will change. Since drift is higher at extreme temperatures, the compensation may not be needed until the temperature is greater than 20C from T0. A sample curve of the ATR setting vs. Frequency Adjustment for the ISL1220 and a typical RTC crystal is given in Figure 18. This curve may vary with different crystals, so it is good practice to evaluate a given crystal in an ISL1220 circuit before establishing the adjustment values.
90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0
Do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. These logic level lines can induce noise in the oscillator circuit to cause misclocking. Add a ground trace around the crystal with one end terminated at the chip ground. This will provide termination for emitted noise in the vicinity of the RTC device.
FIGURE 19. SUGGESTED LAYOUT FOR ISL1220 AND CRYSTAL
PPM ADJUSTMENT
In addition, it is a good idea to avoid a ground plane under the X1 and X2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit, traces should be routed away from the RTC device as well. The traces for the VBAT and VCC pins can be treated as a ground, and should be routed around the crystal.
Super Capacitor Backup
The ISL1220 device provides a VBAT pin which is used for a battery backup input. A Super Capacitor can be used as an alternative to a battery in cases where shorter backup times are required. Since the battery backup supply current required by the ISL1220 is extremely low, it is possible to get months of backup operation using a Super Capacitor. Typical capacitor values are a few F to 1 Farad or more depending on the application. If backup is only needed for a few minutes, then a small inexpensive electrolytic capacitor can be used. For extended periods, a low leakage, high capacity Super Capacitor is the best choice. These devices are available from such vendors as Panasonic and Murata. The main specifications include working voltage and leakage current. If the application is for charging the capacitor from a +5V 5% supply with a signal diode, then the voltage on the capacitor can vary from ~4.5V to slightly over 5.0V. A capacitor with a rated WV of 5.0V may have a reduced lifetime if the supply voltage is slightly high. The leakage current should be as small as possible. For example, a Super Capacitor should be specified with leakage of well below 1A. A standard electrolytic capacitor with DC leakage current in the microamps will have a severely shortened backup time. Below are some examples with equations to assist with calculating backup times and required capacitance for the ISL1220 device. The backup supply current plays a major
0
5
10 15 20 25 30 35 40 45 50 55 60 ATR SETTING
FIGURE 18. ATR SETTING vs OSCILLATOR FREQUENCY ADJUSTMENT
This curve is then used to figure what ATR and DTR settings are used for compensation. The results would be placed in a lookup table for the microcontroller to access.
Layout Considerations
The crystal input at X1 has a very high impedance, and oscillator circuits operating at low frequencies such as 32.768kHz are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking. Figure 19 shows a suggested layout for the ISL1220 device using a surface mount crystal. Two main precautions should be followed:
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part in these equations, and a typical value was chosen for example purposes. For a robust design, a margin of 30% should be included to cover supply current and capacitance tolerances over the results of the calculations. Even more margin should be included if periods of very warm temperature operation are expected. Combining with Equation 2 gives the equation for backup time: TBACKUP = CBAT * (VBAT2 - VBAT1) / (IBATAVG + ILKG) seconds (EQ. 5) where CBAT = 0.47F VBAT2 = 4.7V VBAT1 = 1.8V ILKG = 0 (assumed minimal)
2.7V to 5.5V VCC VBAT CBAT
GND
Example 1. Calculating Backup Time Given Voltages and Capacitor Value
1N4148
Solving equation 4 for this example, IBATAVG = 4.387E-7 A TBACKUP = 0.47 * (2.9) / 4.38E-7 = 3.107E6 sec Since there are 86,400 seconds in a day, this corresponds to 35.96 days. If the 30% tolerance is included for capacitor and supply current tolerances, then worst case backup time would be: CBAT = 0.70 * 35.96 = 25.2 days
FIGURE 20. SUPERCAPACITOR CHARGING CIRCUIT
In Figure 20, use CBAT = 0.47F and VCC = 5.0V. With VCC = 5.0V, the voltage at VBAT will approach 4.7V as the diode turns off completely. The ISL1220 is specified to operate down to VBAT = 1.8V. The capacitance charge/discharge equation is used to estimate the total backup time: I = CBAT * dV/dT Rearranging gives: dT = CBAT * dV/ITOT to solve for backup time.
(EQ. 2) (EQ. 1)
Example 2. Calculating a Capacitor Value for a Given Backup Time
Referring to Figure 20 again, the capacitor value needs to be calculated to give 2 months (60 days) of backup time, given VCC = 5.0V. As in Example 1, the VBAT voltage will vary from 4.7V down to 1.8V. We will need to rearrange Equation 2 to solve for capacitance: CBAT = dT*I/dV
(EQ. 6)
CBAT is the backup capacitance and dV is the change in voltage from fully charged to loss of operation. Note that ITOT is the total of the supply current of the ISL1220 (IBAT) plus the leakage current of the capacitor and the diode, ILKG. In these calculations, ILKG is assumed to be extremely small and will be ignored. If an application requires extended operation at temperatures over 50C, these leakages will increase and hence reduce backup time. Note that IBAT changes with VBAT almost linearly (see Typical Performance Curves). This allows us to make an approximation of IBAT, using a value midway between the two endpoints. The typical linear equation for IBAT vs VBAT is: IBAT = 1.031E-7*(VBAT) + 1.036E-7 Amps
(EQ. 3)
Using the terms described above, this equation becomes: CBAT = TBACKUP * (IBATAVG + ILKG)/(VBAT2 - VBAT1)
(EQ. 7)
where: TBACKUP = 60 days * 86,400 sec/day = 5.18 E6 sec IBATAVG = 4.387 E-7 A (same as Example 1) ILKG = 0 (assumed) VBAT2 = 4.7V VBAT1 = 1.8V Solving gives: CBAT = 5.18 E6 * (4.387 E-7)/(2.9) = 0.784F If the 30% tolerance is included for tolerances, then worst case cap value would be: CBAT = 1.3 *.784 = 1.02F
Using this equation to solve for the average current given 2 voltage points gives: IBATAVG = 5.155E-8*(VBAT2 + VBAT1) + 1.036E-7 Amps
(EQ. 4)
19
FN6315.0 June 22, 2006
ISL1220 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o 15o 6o MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028 A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN6315.0 June 22, 2006

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